module TB (
    
);

reg clk;
reg RST;

initial begin
    clk = 0;
    forever begin
        #1 clk = ~clk;
    end
end

initial begin
    RST = 1;
    #2 RST = 0;
end

CPUTOP u_CPUTOP(
    .clk (clk ),
    .RST (RST )
);

    
endmodule